WebAssembly is an open, industry-wide effort to bring a safe, efficient assembly language to the web. WebAssembly technology is developed collaboratively by major browser vendors including Mozilla, Google, Microsoft, and Apple. WebAssembly modules can be downloaded and executed by the majority of browsers in use today.
Proposal to add garbage collection (GC) support.
This is a phase 1 proposal and may change in future. [As of 2022]
Multibyte instructions beginning with 0xFC.
SIMD (single instruction, multiple data) instructions begin with 0xFD.
Multibyte instructions beginning with 0xFE.
The unreachable instruction causes an unconditional trap.
A trap immediately aborts execution. Traps cannot be handled by WebAssembly code, but are reported to the outside environment, where they typically can be caught.
Followed by:
Note: Any instructions following must be valid.
Stack:
[t∗1] → [t∗2]
stack-polymorphic: performs an unconditional control transfer.
The nop instruction does nothing.
Stack:
[] → []
[t?]
the beginning of a block construct, a sequence of instructions with a label at the end.
Followed by:
- i8 rt : blocktype — 0x40 = [], 0x7F = [i32], 0x7E = [i64], 0x7D = [f32], 0x7C = [f64]
- instructions
- 0x0B — end
Stack:
[] → [t∗]
The result type of the instructions must match the blocktype.
The block, loop and if instructions are structured instructions. They bracket nested sequences of instructions, called blocks, terminated with, or separated by, end or else pseudo-instructions. They must be well-nested.
[t?]
a block with a label at the beginning which may be used to form loops
Followed by:
- i8 rt : blocktype — 0x40 = [], 0x7F = [i32], 0x7E = [i64], 0x7D = [f32], 0x7C = [f64]
- instructions
- 0x0B — end
Stack:
[] → [t∗]
[t?]
the beginning of an if construct with an implicit then block
Followed by:
- i8 rt : blocktype — 0x40 = [], 0x7F = [i32], 0x7E = [i64], 0x7D = [f32], 0x7C = [f64]
- instructions1
- 0x0B — end
or
- i8 rt : blocktype
- instructions1
- 0x05 — else
- instructions2
- 0x0B — end
Stack:
[i32] → [t∗]
i32 c → [t∗]
if c is non-zero, enter block instructions1, else enter block instructions2
Marks the else block of an if.
begins a block which can handle thrown exceptions
Exception Handling Proposal
begins the catch block of the try block
Exception Handling Proposal
Creates an exception defined by the tag and then throws it
Exception Handling Proposal
Pops the exnref on top of the stack and throws it
Exception Handling Proposal
Pops the exnref on top of the stack and throws it
Exception Handling Proposal
Marks the end of a block, loop, if, or function.
l
Branch to a given label in an enclosing construct.
Performs an unconditional branch.
Followed by:
u32 l : labelidx
Label 0 refers to the innermost structured control instruction enclosing the referring branch instruction, while increasing indices refer to those farther out.
Stack:
[t∗1 t?] → [t∗2]
A branch targeting a block or if behaves like a break statement in most C-like languages, while a branch targeting a loop behaves like a continue statement.
stack-polymorphic: performs an unconditional control transfer.
l
Performs a conditional branch, branching if i32 c is non-zero.
Conditionally branch to a given label in an enclosing construct.
Followed by:
u32 l : labelidx
Stack:
[t? i32] → [t?]
l* l
A jump table which jumps to a label in an enclosing construct.
Performs an indirect branch through an operand indexing into the label vector that is an immediate to the instruction, or to a default target if the operand is out of bounds.
Followed by:
- u32 l* : vec( labelidx )
- u32 l : labelidx
Stack:
[t∗1 t? i32] → [t∗2]
stack-polymorphic: performs an unconditional control transfer.
return zero or more values from this function.
The return instruction is a shortcut for an unconditional branch to the outermost block, which implicitly is the body of the current function.
Stack:
[t∗1 t?] → [t∗2]
stack-polymorphic: performs an unconditional control transfer.
x
The call instruction invokes another function, consuming the necessary arguments from the stack and returning the result values of the call.
Followed by:
u32 x : funcidx
Stack:
[t∗1] → [t∗2]
x
The call_indirect instruction calls a function indirectly through an operand indexing into a table.
Followed by:
- u32 x : typeidx
- 0x00 — zero byte
Stack:
[t? i32] → [t?]
In future versions of WebAssembly, the zero byte may be used to index additional tables.
the tail-call version of call
Tail calls proposal
the tail-call version of call
Tail calls proposal
call a function through a ref $t
Typed Function References Proposal
Typed Function References Proposal
begins the delegate block of the try block
Exception Handling Proposal
begins the catch_all block of the try block
Exception Handling Proposal
The drop instruction simply throws away a single operand.
Stack:
[t] → [] (value-polymorphic)
The select instruction selects one of its first two operands based on whether its third operand is zero or not.
Stack:
[t t i32] → [t] (value-polymorphic)
Only annotated 'select' can be used with reference types.
Reference Types Proposal
begins a block which can handle thrown exceptions
Exception Handling Proposal
x
This instruction gets the value of a variable.
Followed by:
u32 x : localidx
Stack:
[] → [t]
The index space for locals is only accessible inside a function and includes the parameters of that function, which precede the local variables.
The locals context refers to the list of locals declared in the current function (including parameters), represented by their value type.
x
This instruction sets the value of a variable.
Followed by:
u32 x : localidx
Stack:
[t] → []
The index space for locals is only accessible inside a function and includes the parameters of that function, which precede the local variables.
x
The local.tee instruction is like local.set but also returns its argument.
Followed by:
u32 x : localidx
Stack:
[t] → [t]
The index space for locals is only accessible inside a function and includes the parameters of that function, which precede the local variables.
x
This instruction gets the value of a variable.
Followed by:
u32 x : globalidx
Stack:
[] → [t]
The globals context is the list of globals declared in the current module, represented by their global type.
x
This instruction sets the value of a variable
Followed by:
u32 x : globalidx
Stack:
[t] → []
Access tables
Reference Types Proposal
Access tables
Reference Types Proposal
m
load 4 bytes as i32.
Followed by:
m : memarg { u32 offset, u32 align }
Stack:
[i32] → [i32]
i : address-operand → c : result
Memory is accessed with load and store instructions for the different value types. They all take a memory immediate memarg that contains an address offset and the expected alignment.
The immediate value memarg.align is an alignment hint about the effective-address. It is a power-of 2 encoded as log2(memarg.align). In practice, its value may be: 0 (8-bit), 1 (16-bit), 2 (32-bit), or (64-bit; used only with wasm64).
effective-address = address-operand + memarg.offset
If memarg.align is incorrect it is considered "misaligned". Misaligned access still has the same behavior as aligned access, only possibly much slower.
m
load 8 bytes as i64.
Followed by:
m : memarg { u32 offset, u32 align }
Stack:
[i32] → [i64]
The static address offset is added to the dynamic address operand, yielding a 33 bit effective address that is the zero-based index at which the memory is accessed. All values are read and written in little endian byte order. A trap results if any of the accessed memory bytes lies outside the address range implied by the memory’s current size.
m
load 4 bytes as f32.
Stack:
[i32] → [f32]
Note: When a number is stored into memory, it is converted into a sequence of bytes in little endian byte order.
m
load 8 bytes as f64.
Stack:
[i32] → [f64]
m
load 1 byte and sign-extend i8 to i32.
Stack:
[i32] → [i32]
Integer loads and stores can optionally specify a storage size that is smaller than the bit width of the respective value type. In the case of loads, a sign extension mode sx (s|u) is then required to select appropriate behavior.
m
load 1 byte and zero-extend i8 to i32
Stack:
[i32] → [i32]
m
load 2 bytes and sign-extend i16 to i32
Stack:
[i32] → [i32]
m
load 2 bytes and zero-extend i16 to i32
Stack:
[i32] → [i32]
m
load 1 byte and sign-extend i8 to i64
Stack:
[i32] → [i64]
m
load 1 byte and zero-extend i8 to i64
Stack:
[i32] → [i64]
m
load 2 bytes and sign-extend i16 to i64
Stack:
[i32] → [i64]
m
load 2 bytes and zero-extend i16 to i64
Stack:
[i32] → [i64]
m
load 4 bytes and sign-extend i16 to i64
Stack:
[i32] → [i64]
m
load 4 bytes and zero-extend i16 to i64
Stack:
[i32] → [i64]
m
store 4 bytes (no conversion)
Stack:
[i32 i32] → []
m
store 8 bytes (no conversion)
Stack:
[i32 i64] → []
m
store 4 bytes (no conversion)
Stack:
[i32 f32] → []
m
store 8 bytes (no conversion)
Stack:
[i32 f64] → []
m
wrap i32 to i8 and store 1 byte
Stack:
[i32 i32] → []
m
wrap i32 to i16 and store 2 bytes
Stack:
[i32 i32] → []
m
wrap i64 to i8 and store 1 byte
Stack:
[i32 i64] → []
m
wrap i64 to i16 and store 2 bytes
Stack:
[i32 i64] → []
m
wrap i64 to i32 and store 4 bytes
Stack:
[i32 i64] → []
The memory.size instruction returns the current size of a memory.
Operates in units of page size. Each page is 65,536 bytes (64KB).
Stack:
[] → [i32]
The memory.grow instruction grows memory by a given delta and returns the previous size, or −1 if enough memory cannot be allocated.
Operates in units of page size. Each page is 65,536 bytes (64KB).
Stack:
[i32] → [i32]
n
Push a 32-bit integer value to the stack.
Followed by:
n : i32
Stack:
[] → [i32]
n
Push a 64-bit integer value to the stack.
Followed by:
n : i64
Stack:
[] → [i64]
z
Push a 32-bit float value to the stack.
Followed by:
z : f32
Stack:
[] → [f32]
Push a 64-bit float value to the stack.
z
Followed by:
z : f64
Stack:
[] → [f64]
compare equal to zero.
Return 1 if operand is zero, 0 otherwise.
Stack:
[i32] → [i32]
compare equal to zero.
Return 1 if operand is zero, 0 otherwise.
Stack:
[i64] → [i32]
==
sign-agnostic compare equal
Stack:
[i32 i32] → [i32]
==
sign-agnostic compare equal
Stack:
[i64 i64] → [i32]
≠
sign-agnostic compare unequal
Stack:
[i32 i32] → [i32]
≠
sign-agnostic compare unequal
Stack:
[i64 i64] → [i32]
<
signed less than
Stack:
[i32 i32] → [i32]
<
signed less than
Stack:
[i64 i64] → [i32]
<
unsigned less than
Stack:
[i32 i32] → [i32]
<
unsigned less than
Stack:
[i64 i64] → [i32]
>
signed greater than
Stack:
[i32 i32] → [i32]
>
signed greater than
Stack:
[i64 i64] → [i32]
>
unsigned greater than
Stack:
[i32 i32] → [i32]
>
unsigned greater than
Stack:
[i64 i64] → [i32]
≤
signed less than or equal
Stack:
[i32 i32] → [i32]
≤
signed less than or equal
Stack:
[i64 i64] → [i32]
≤
unsigned less than or equal
Stack:
[i32 i32] → [i32]
≤
unsigned less than or equal
Stack:
[i64 i64] → [i32]
≥
signed greater than or equal
Stack:
[i32 i32] → [i32]
≥
signed greater than or equal
Stack:
[i64 i64] → [i32]
≥
unsigned greater than or equal
Stack:
[i32 i32] → [i32]
≥
unsigned greater than or equal
Stack:
[i64 i64] → [i32]
==
compare equal
Stack:
[f32 f32] → [i32]
==
compare equal
Stack:
[f64 f64] → [i32]
≠
compare unordered or unequal
Stack:
[f32 f32] → [i32]
≠
compare unordered or unequal
Stack:
[f64 f64] → [i32]
<
less than
Stack:
[f32 f32] → [i32]
<
less than
Stack:
[f64 f64] → [i32]
>
greater than
Stack:
[f32 f32] → [i32]
>
greater than
Stack:
[f64 f64] → [i32]
≤
less than or equal
Stack:
[f32 f32] → [i32]
≤
less than or equal
Stack:
[f64 f64] → [i32]
≥
greater than or equal
Stack:
[f32 f32] → [i32]
≥
greater than or equal
Stack:
[f64 f64] → [i32]
sign-agnostic count leading zero bits
Return the count of leading zero bits in i. All zero bits are considered leading if the value is zero.
Stack:
[i32] → [i32]
sign-agnostic count leading zero bits
Return the count of leading zero bits in i. All zero bits are considered leading if the value is zero.
Stack:
[i64] → [i64]
sign-agnostic count trailing zero bits
Return the count of trailing zero bits in i. All zero bits are considered trailing if the value is zero.
Stack:
[i32] → [i32]
sign-agnostic count trailing zero bits
Return the count of trailing zero bits in i. All zero bits are considered trailing if the value is zero.
Stack:
[i64] → [i64]
sign-agnostic count number of one bits
Return the count of non-zero bits in i.
Stack:
[i32] → [i32]
sign-agnostic count number of one bits
Return the count of non-zero bits in i.
Stack:
[i64] → [i64]
sign-agnostic addition
Stack:
[i32 i32] → [i32]
sign-agnostic addition
Stack:
[i64 i64] → [i64]
sign-agnostic subtraction
Stack:
[i32 i32] → [i32]
sign-agnostic subtraction
Stack:
[i64 i64] → [i64]
sign-agnostic multiplication, modulo 232
Stack:
[i32 i32] → [i32]
sign-agnostic multiplication, modulo 264
Stack:
[i64 i64] → [i64]
signed division (result is truncated toward zero)
Stack:
[i32 i32] → [i32]
signed division (result is truncated toward zero)
Stack:
[i64 i64] → [i64]
unsigned division (result is floored)
Stack:
[i32 i32] → [i32]
unsigned division (result is floored)
Stack:
[i64 i64] → [i64]
signed remainder (result has the sign of the dividend)
Stack:
[i32 i32] → [i32]
signed remainder (result has the sign of the dividend)
Stack:
[i64 i64] → [i64]
unsigned remainder
Stack:
[i32 i32] → [i32]
unsigned remainder
Stack:
[i64 i64] → [i64]
sign-agnostic bitwise and.
Return the bitwise conjunction of 𝑖1 and 𝑖2.
Stack:
[i32 i32] → [i32]
sign-agnostic bitwise and.
Return the bitwise conjunction of 𝑖1 and 𝑖2.
Stack:
[i64 i64] → [i64]
sign-agnostic bitwise inclusive or.
Return the bitwise disjunction of 𝑖1 and 𝑖2.
Stack:
[i32 i32] → [i32]
sign-agnostic bitwise inclusive or.
Return the bitwise disjunction of 𝑖1 and 𝑖2.
Stack:
[i64 i64] → [i64]
sign-agnostic bitwise exclusive or.
Return the bitwise exclusive disjunction of 𝑖1 and 𝑖2.
Stack:
[i32 i32] → [i32]
sign-agnostic bitwise exclusive or.
Return the bitwise exclusive disjunction of 𝑖1 and 𝑖2.
Stack:
[i64 i64] → [i64]
sign-agnostic shift left
Return the result of shifting i1 left by k bits, modulo 232
Stack:
[i32 i32] → [i32]
sign-agnostic shift left
Return the result of shifting i1 left by k bits, modulo 264
Stack:
[i64 i64] → [i64]
sign-replicating (arithmetic) shift right
Return the result of shifting i1 right by k bits, extended with the most significant bit of the original value.
Stack:
[i32 i32] → [i32]
sign-replicating (arithmetic) shift right
Return the result of shifting i1 right by k bits, extended with the most significant bit of the original value.
Stack:
[i64 i64] → [i64]
zero-replicating (logical) shift right
Return the result of shifting i1 right by k bits, extended with 0 bits.
Stack:
[i32 i32] → [i32]
zero-replicating (logical) shift right
Return the result of shifting i1 right by k bits, extended with 0 bits.
Stack:
[i64 i64] → [i64]
sign-agnostic rotate left
Return the result of rotating i1 left by k bits.
Stack:
[i32 i32] → [i32]
sign-agnostic rotate left
Return the result of rotating i1 left by k bits.
Stack:
[i64 i64] → [i64]
sign-agnostic rotate right
Return the result of rotating i1 right by k bits.
Stack:
[i32 i32] → [i32]
sign-agnostic rotate right
Return the result of rotating i1 right by k bits.
Stack:
[i64 i64] → [i64]
absolute value
Stack:
[f32] → [f32]
absolute value
Stack:
[f64] → [f64]
negation
Stack:
[f32] → [f32]
negation
Stack:
[f64] → [f64]
ceiling operator
Stack:
[f32] → [f32]
ceiling operator
Stack:
[f64] → [f64]
floor operator
Stack:
[f32] → [f32]
floor operator
Stack:
[f64] → [f64]
round to nearest integer towards zero
Stack:
[f32] → [f32]
round to nearest integer towards zero
Stack:
[f64] → [f64]
round to nearest integer, ties to even
Stack:
[f32] → [f32]
round to nearest integer, ties to even
Stack:
[f64] → [f64]
square root
Stack:
[f32] → [f32]
square root
Stack:
[f64] → [f64]
addition
Stack:
[f32 f32] → [f32]
addition
Stack:
[f64 f64] → [f64]
subtraction
Stack:
[f32 f32] → [f32]
subtraction
Stack:
[f64 f64] → [f64]
multiplication
Stack:
[f32 f32] → [f32]
multiplication
Stack:
[f64 f64] → [f64]
division
partial function: division by 0 is undefined
Stack:
[f32 f32] → [f32]
division
partial function: division by 0 is undefined
Stack:
[f64 f64] → [f64]
minimum (binary operator); if either operand is NaN, returns NaN
Stack:
[f32 f32] → [f32]
minimum (binary operator); if either operand is NaN, returns NaN
Stack:
[f64 f64] → [f64]
maximum (binary operator); if either operand is NaN, returns NaN
Stack:
[f32 f32] → [f32]
maximum (binary operator); if either operand is NaN, returns NaN
Stack:
[f64 f64] → [f64]
If z1 and z2 have the same sign, then return z1. Else return z1 with negated sign.
Stack:
[f32 f32] → [f32]
If z1 and z2 have the same sign, then return z1. Else return z1 with negated sign.
Stack:
[f64 f64] → [f64]
wrap a 64-bit integer to a 32-bit integer.
Return i modulo 232.
Stack:
[i64] → [i32]
truncate a 32-bit float to a signed 32-bit integer
Stack:
[f32] → [i32]
truncate a 32-bit float to an unsigned 32-bit integer
Stack:
[f32] → [i32]
truncate a 64-bit float to a signed 32-bit integer
Stack:
[f64] → [i32]
truncate a 64-bit float to an unsigned 32-bit integer
Stack:
[f64] → [i32]
extend a signed 32-bit integer to a 64-bit integer.
Stack:
[i32] → [i64]
extend an unsigned 32-bit integer to a 64-bit integer.
Stack:
[i32] → [i64]
truncate a 32-bit float to a signed 64-bit integer.
Stack:
[f32] → [i64]
truncate a 32-bit float to an unsigned 64-bit integer.
Stack:
[f32] → [i64]
truncate a 64-bit float to a signed 64-bit integer.
Stack:
[f64] → [i64]
truncate a 64-bit float to an unsigned 64-bit integer.
Stack:
[f64] → [i64]
convert a signed 32-bit integer to a 32-bit float.
Stack:
[i32] → [f32]
convert an unsigned 32-bit integer to a 32-bit float.
Stack:
[i32] → [f32]
convert a signed 64-bit integer to a 32-bit float.
Stack:
[i64] → [f32]
convert an unsigned 64-bit integer to a 32-bit float.
Stack:
[i64] → [f32]
demote a 64-bit float to a 32-bit float
Stack:
[f64] → [f32]
convert a signed 32-bit integer to a 64-bit float.
Stack:
[i32] → [f64]
convert an unsigned 32-bit integer to a 64-bit float.
Stack:
[i32] → [f64]
convert a signed 64-bit integer to a 64-bit float.
Stack:
[i64] → [f64]
convert an unsigned 64-bit integer to a 64-bit float.
Stack:
[i64] → [f64]
promote a 32-bit float to a 64-bit float
Stack:
[f32] → [f64]
reinterpret the bits of a 32-bit float as a 32-bit integer
Stack:
[f32] → [i32]
reinterpret the bits of a 64-bit float as a 64-bit integer
Stack:
[f64] → [i64]
reinterpret the bits of a 32-bit integer as a 32-bit float
Stack:
[i32] → [f32]
reinterpret the bits of a 64-bit integer as a 64-bit float
Stack:
[i64] → [f64]
extend a signed 8-bit integer to a 32-bit integer
Sign-extension operators extension
extend a signed 16-bit integer to a 32-bit integer
Sign-extension operators extension
extend a signed 8-bit integer to a 64-bit integer
Sign-extension operators extension
extend a signed 16-bit integer to a 64-bit integer
Sign-extension operators extension
extend a signed 32-bit integer to a 64-bit integer
Sign-extension operators extension
evaluates to the null reference constant
Reference Types Proposal
checks for null
Reference Types Proposal
creates a reference to a given function
Reference Types Proposal
converts a nullable reference to a non-nullable one or traps if null
Typed Function References Proposal
converts a nullable reference to a non-nullable one or branches if null
Typed Function References Proposal
[eqref eqref] -> [i32]
Reference Types Proposal
checks for null and branches if present
Typed Function References Proposal, GC Proposal
Multibyte instructions beginning with the prefix 0xFB.
- Proposal to add garbage collection (GC) support.
- Proposal to add reference-typed strings.
See table below for full opcodes.
Multibyte instructions beginning with the prefix 0xFC.
Includes opcodes from the following extensions:
- Non-trapping float-to-int conversion
- Bulk Memory Operations
- Reference Types Proposal
See table below for full opcodes.
Multibyte instructions beginning with the prefix 0xFD.
SIMD opcodes (Vector instructions).
The opcode which follows the prefix uses variable-length integer encoding (LEB128)
See table below for full opcodes.
Multibyte instructions beginning with the prefix 0xFE.
Threads Proposal for WebAssembly.
See table below for full opcodes.
allocates a structure with canonical RTT (runtime type) and initialises its fields with given values
Garbage Collection Proposal
allocates a structure of type $t with canonical RTT (runtime type) and initialises its fields with default values
Garbage Collection Proposal
reads field i
from a structure
Garbage Collection Proposal
writes field i
of a structure
Garbage Collection Proposal
allocates an array with canonical RTT (runtime type)
Garbage Collection Proposal
allocates an array with canonical RTT (runtime type) and initialises its fields with the default value
Garbage Collection Proposal
reads an element from an array
Garbage Collection Proposal
writes an element to an array
Garbage Collection Proposal
inquires the length of an array
Garbage Collection Proposal
allocates an array with canonical RTT (runtime type) of fixed size and initialises it from operands
Garbage Collection Proposal
allocates an array with canonical RTT (runtime type) and initialises it from a data segment
Garbage Collection Proposal
allocates an array with canonical RTT (runtime type) and initialises it from an element segment
Garbage Collection Proposal
creates an i31ref from a 32 bit value, truncating high bit
Garbage Collection Proposal
extracts the value, sign-extending
Garbage Collection Proposal
extracts the value, zero-extending
Garbage Collection Proposal
checks whether a reference has a given heap type
Garbage Collection Proposal
checks whether a reference has a given heap type
Garbage Collection Proposal
tries to convert to a given heap type
Garbage Collection Proposal
branches if a reference has a given heap type
Garbage Collection Proposal
branches if a reference does not have a given heap type
Garbage Collection Proposal
checks whether a reference has a given heap type
Garbage Collection Proposal
tries to convert to a given heap type
Garbage Collection Proposal
branches if a reference has a given heap type
Garbage Collection Proposal
branches if a reference does not have a given heap type
Garbage Collection Proposal
converts an external value into the internal representation
Garbage Collection Proposal
converts an internal value into the external representation
Garbage Collection Proposal
saturating form of i32.trunc_f32_s
Non-trapping float-to-int Conversion Proposal
saturating form of i32.trunc_f32_u
Non-trapping float-to-int Conversion Proposal
saturating form of i32.trunc_f64_s
Non-trapping float-to-int Conversion Proposal
saturating form of i32.trunc_f64_u
Non-trapping float-to-int Conversion Proposal
saturating form of i64.trunc_f32_s
Non-trapping float-to-int Conversion Proposal
saturating form of i64.trunc_f32_u
Non-trapping float-to-int Conversion Proposal
saturating form of i64.trunc_f64_s
Non-trapping float-to-int Conversion Proposal
saturating form of i64.trunc_f64_u
Non-trapping float-to-int Conversion Proposal
copy from a passive data segment to linear memory
Bulk Memory Operations
prevent further use of passive data segment
Bulk Memory Operations
manipulate the size of a table
Reference Types Proposal
manipulate the size of a table
Reference Types Proposal
fills a range in a table with a value
Reference Types Proposal
copy from one region of linear memory to another region
Bulk Memory Operations
fill a region of linear memory with a given byte value
Bulk Memory Operations
copy from a passive element segment to a table
Bulk Memory Operations
prevent further use of a passive element segment
Bulk Memory Operations
copy from one region of a table to another region
Bulk Memory Operations
Calculates the absolute value of each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.
Lane-wise addition of two 128-bit vectors interpreted as four 32-bit floating point numbers.
Lane-wise rounding to the nearest integral value not smaller than the input.
Converts a 128-bit vector interpreted as four 32-bit unsigned integers into a 128-bit vector of four 32-bit floating point numbers.
Converts a 128-bit vector interpreted as four 32-bit signed integers into a 128-bit vector of four 32-bit floating point numbers.
Conversion of the two double-precision floating point lanes to two lower single-precision lanes of the result. The two higher lanes of the result are initialized to zero. If the conversion result is not representable as a single-precision floating point number, it is rounded to the nearest-even representable number.
Lane-wise division of two 128-bit vectors interpreted as four 32-bit floating point numbers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.
Returns a new vector where each lane is all ones if the corresponding input elements were equal, or all zeros otherwise.
Extracts a lane from a 128-bit vector interpreted as 4 packed f32 numbers.
Extracts the scalar value of lane specified fn the immediate mode operand N from a. If N is out of bounds then it is a compile time error.
Lane-wise rounding to the nearest integral value not greater than the input.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is greater than [or equal] the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is greater than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is less than [or equal] the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is less than the right element, or all zeros otherwise.
Calculates the lane-wise [maximum] of two 128-bit vectors interpreted as four 32-bit floating point numbers.
Calculates the lane-wise minimum of two 128-bit vectors interpreted as four 32-bit floating point numbers.
Lane-wise multiplication of two 128-bit vectors interpreted as four 32-bit floating point numbers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit floating point numbers.
Returns a new vector where each lane is all ones if the corresponding input elements were not equal, or all zeros otherwise.
Lane-wise rounding to the nearest integral value; if two values are equally near, rounds to the even one.
Negates each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.
Lane-wise maximum value, defined as a < b ? b : a
Lane-wise minimum value, defined as b < a ? b : a
Replaces a lane from a 128-bit vector interpreted as 4 packed f32 numbers.
Rust: fn f32x4_replace_lane(a: v128, val: f32) -> v128
Replaces the scalar value of lane specified fn the immediate mode operand N
from a
. If N
is out of bounds then it is a compile time error.
Creates a vector with identical lanes.
Constructs a vector with x replicated to all 4 lanes.
Calculates the square root of each lane of a 128-bit vector interpreted as four 32-bit floating point numbers.
Lane-wise subtraction of two 128-bit vectors interpreted as four 32-bit floating point numbers.
Lane-wise rounding to the nearest integral value with the magnitude not larger than the input.
Calculates the absolute value of each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.
Lane-wise add of two 128-bit vectors interpreted as two 64-bit floating point numbers.
Lane-wise rounding to the nearest integral value not smaller than the input.
Lane-wise conversion from signed integer to floating point.
Lane-wise conversion from unsigned integer to floating point.
Lane-wise divide of two 128-bit vectors interpreted as two 64-bit floating point numbers.
Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.
Returns a new vector where each lane is all ones if the corresponding input elements were equal, or all zeros otherwise.
Extracts a lane from a 128-bit vector interpreted as 2 packed f64 numbers.
Extracts the scalar value of lane specified fn the immediate mode operand N from 'a'. If 'N' [is] out of bounds then it is a compile time error.
Lane-wise rounding to the nearest integral value not greater than the input.
Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is greater than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is greater than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers
Returns a new vector where each lane is all ones if the lane-wise left element is less than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.
Returns a new vector where each lane is all ones if the lane-wise left element is less than the right element, or all zeros otherwise.
Calculates the lane-wise maximum of two 128-bit vectors interpreted as two 64-bit floating point numbers.
Calculates the lane-wise minimum of two 128-bit vectors interpreted as two 64-bit floating point numbers.
Lane-wise multiply of two 128-bit vectors interpreted as two 64-bit floating point numbers.
Compares two 128-bit vectors as if they were two vectors of 2 sixty-four-bit floating point numbers.
Returns a new vector where each lane is all ones if the corresponding input elements were not equal, or all zeros otherwise.
Lane-wise rounding to the nearest integral value; if two values are equally near, rounds to the even one.
Negates each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.
Conversion of the two lower single-precision floating point lanes to the two double-precision lanes of the result.
Replaces a lane from a 128-bit vector interpreted as 2 packed f64 numbers.
Replaces the scalar value of lane specified in the immediate mode operand N from 'a'. If N is out of bounds then it is a compile time error.
Creates a vector with identical lanes.
Constructs a vector with x replicated to all 2 lanes.
Calculates the square root of each lane of a 128-bit vector interpreted as two 64-bit floating point numbers.
Lane-wise subtract of two 128-bit vectors interpreted as two 64-bit floating point numbers.
Lane-wise rounding to the nearest integral value with the magnitude not larger than the input.
Lane-wise wrapping absolute value.
Adds two 128-bit vectors as if they were two packed sixteen 8-bit integers.
Adds two 128-bit vectors as if they were two packed sixteen 8-bit signed integers, saturating on overflow to i8::MAX.
Returns true if all lanes are non-zero, false otherwise.
Extracts the high bit for each lane in a and produce a scalar mask with all bits concatenated.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit integers.
Returns a new vector where each lane is all ones if the corresponding input elements were equal, or all zeros otherwise.
Rust: fn i8x16_extract_lane<const N: usize>(a: v128) -> i8
Extracts a lane from a 128-bit vector interpreted as 16 packed i8 numbers.
Extracts the scalar value of lane specified in the immediate mode operand N
from a
. If N
is out of bounds then it is a compile time error.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.
Returns a new vector where each lane is all ones if the lane-wise left element is greater than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.
Returns a new vector where each lane is all ones if the lane-wise left element is greater than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.
Returns a new vector where each lane is all ones if the lane-wise left element is less than the right element, or all zeros otherwise.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit signed integers.
Returns a new vector where each lane is all ones if the lane-wise left element is less than the right element, or all zeros otherwise.
Compares lane-wise signed integers, and returns the maximum of each pair.
Compares lane-wise signed integers, and returns the minimum of each pair.
Converts two input vectors into a smaller lane vector by narrowing each lane.
Signed saturation to 0x7f or 0x80 is used and the input lanes are always interpreted as signed integers.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit integers.
Returns a new vector where each lane is all ones if the corresponding input elements were not equal, or all zeros otherwise.
Negates a 128-bit vectors interpreted as sixteen 8-bit signed integers
Count the number of bits set to one within each lane.
Replaces a lane from a 128-bit vector interpreted as 16 packed i8 numbers.
Replaces the scalar value of lane specified in the immediate mode operand N from 'a'. If N is out of bounds then it is a compile time error.
Shifts each lane to the left by the specified number of bits.
Only the low bits of the shift amount are used if the shift amount is greater than the lane width.
Shifts each lane to the right by the specified number of bits, sign extending.
Only the low bits of the shift amount are used if the shift amount is greater than the lane width.
Returns a new vector with lanes selected from the lanes of the two input vectors $a and $b specified in the 16 immediate operands.
Creates a vector with identical lanes.
Constructs a vector with x replicated to all 16 lanes.
Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit integers.
Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit signed integers, saturating on overflow to i8::MIN.
Returns a new vector with lanes selected from the lanes of the first input vector a specified in the second input vector s.
The indices i in range [0, 15] select the i-th element of 'a'. For indices outside of the range the resulting lane is 0.
Lane-wise wrapping absolute value.
Adds two 128-bit vectors as if they were two packed eight 16-bit integers.
Adds two 128-bit vectors as if they were two packed eight 16-bit signed integers, saturating on overflow to i16::MAX.
Returns true if all lanes are non-zero, false otherwise.
Extracts the high bit for each lane in a and produce a scalar mask with all bits concatenated.
Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit integers.
Integer extended pairwise addition producing extended results (twice wider results than the inputs).
Converts high half of the smaller lane vector to a larger lane vector, sign extended.
Converts low half of the smaller lane vector to a larger lane vector, sign extended.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Extracts a lane from a 128-bit vector interpreted as 8 packed i16 numbers.
Compares two 128-bit vectors as if they were two vectors of eight 16-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of eight 16-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of eight 16-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of eight 16-bit signed integers.
Compares lane-wise signed integers, and returns the maximum of each pair.
Compares lane-wise signed integers, and returns the minimum of each pair.
Multiplies two 128-bit vectors as if they were two packed eight 16-bit integers.
Converts two input vectors into a smaller lane vector by narrowing each lane.
Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit integers.
Negates a 128-bit vectors interpreted as eight 16-bit signed integers
Rust: fn i16x8_q15mulr_sat(a: v128, b: v128) -> v128
Lane-wise saturating rounding multiplication in Q15 format.
Replaces a lane from a 128-bit vector interpreted as 8 packed i16 numbers.
Shifts each lane to the left by the specified number of bits.
Shifts each lane to the right by the specified number of bits, sign extending.
Same as i8x16_shuffle, except operates as if the inputs were eight 16-bit integers, only taking 8 indices to shuffle.
Indices in the range [0, 7] select from a while [8, 15] select from b. Note that this will generate the i8x16.shuffle instruction, since there is no native i16x8.shuffle instruction (there is no need for one since i8x16.shuffle suffices).
Creates a vector with identical lanes.
Subtracts two 128-bit vectors as if they were two packed eight 16-bit integers.
Subtracts two 128-bit vectors as if they were two packed eight 16-bit signed integers, saturating on overflow to i16::MIN.
Lane-wise wrapping absolute value.
Adds two 128-bit vectors as if they were two packed four 32-bit integers.
Returns true if all lanes are non-zero, false otherwise.
Extracts the high bit for each lane in a and produce a scalar mask with all bits concatenated.
Lane-wise multiply signed 16-bit integers in the two input vectors and add adjacent pairs of the full 32-bit results.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit integers.
Integer extended pairwise addition producing extended results (twice wider results than the inputs).
Converts high half of the smaller lane vector to a larger lane vector, sign extended.
Converts low half of the smaller lane vector to a larger lane vector, sign extended.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Extracts a lane from a 128-bit vector interpreted as 4 packed i32 numbers.
Compares two 128-bit vectors as if they were two vectors of four 32-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of four 32-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of four 32-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit signed integers.
Compares lane-wise signed integers, and returns the maximum of each pair.
Compares lane-wise signed integers, and returns the minimum of each pair.
Multiplies two 128-bit vectors as if they were two packed four 32-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit integers.
Negates a 128-bit vectors interpreted as four 32-bit signed integers
Replaces a lane from a 128-bit vector interpreted as 4 packed i32 numbers.
Shifts each lane to the left by the specified number of bits.
Shifts each lane to the right by the specified number of bits, sign extending.
Creates a vector with identical lanes.
Subtracts two 128-bit vectors as if they were two packed four 32-bit integers.
Converts a 128-bit vector interpreted as four 32-bit floating point numbers into a 128-bit vector of four 32-bit signed integers.
Saturating conversion of the two double-precision floating point lanes to two lower integer lanes using the IEEE convertToIntegerTowardZero function.
Lane-wise wrapping absolute value.
Adds two 128-bit vectors as if they were two packed two 64-bit integers.
Returns true if all lanes are non-zero, false otherwise.
Extracts the high bit for each lane in 'a' and produce a scalar mask with all bits concatenated.
Compares two 128-bit vectors as if they were two vectors of two 64-bit integers.
Converts high half of the smaller lane vector to a larger lane vector, sign extended.
Converts low half of the smaller lane vector to a larger lane vector, sign extended.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Extracts a lane from a 128-bit vector interpreted as 2 packed i64 numbers.
Compares two 128-bit vectors as if they were two vectors of two 64-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of two 64-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of two 64-bit signed integers.
Compares two 128-bit vectors as if they were two vectors of two 64-bit signed integers.
Multiplies two 128-bit vectors as if they were two packed two 64-bit integers.
Compares two 128-bit vectors as if they were two vectors of two 64-bit integers.
Negates a 128-bit vectors interpreted as two 64-bit signed integers
Replaces a lane from a 128-bit vector interpreted as 2 packed i64 numbers.
Shifts each lane to the left by the specified number of bits.
Shifts each lane to the right by the specified number of bits, sign extending.
Creates a vector with identical lanes.
Subtracts two 128-bit vectors as if they were two packed two 64-bit integers.
Adds two 128-bit vectors as if they were two packed sixteen 8-bit unsigned integers, saturating on overflow to u8::MAX.
Lane-wise rounding average.
Extracts a lane from a 128-bit vector interpreted as 16 packed u8 numbers.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 16 eight-bit unsigned integers.
Compares lane-wise unsigned integers, and returns the maximum of each pair.
Compares lane-wise unsigned integers, and returns the minimum of each pair.
Converts two input vectors into a smaller lane vector by narrowing each lane.
Shifts each lane to the right by the specified number of bits, shifting in zeros.
Subtracts two 128-bit vectors as if they were two packed sixteen 8-bit unsigned integers, saturating on overflow to 0.
Adds two 128-bit vectors as if they were two packed eight 16-bit unsigned integers, saturating on overflow to u16::MAX.
Lane-wise rounding average.
Integer extended pairwise addition producing extended results (twice wider results than the inputs).
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Extracts a lane from a 128-bit vector interpreted as 8 packed u16 numbers.
Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 8 sixteen-bit unsigned integers.
Compares lane-wise unsigned integers, and returns the maximum of each pair.
Compares lane-wise unsigned integers, and returns the minimum of each pair.
Converts two input vectors into a smaller lane vector by narrowing each lane.
Shifts each lane to the right by the specified number of bits, shifting in zeros.
Subtracts two 128-bit vectors as if they were two packed eight 16-bit unsigned integers, saturating on overflow to 0.
Integer extended pairwise addition producing extended results (twice wider results than the inputs).
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.
Compares two 128-bit vectors as if they were two vectors of 4 thirty-two-bit unsigned integers.
Compares lane-wise unsigned integers, and returns the maximum of each pair.
Compares lane-wise unsigned integers, and returns the minimum of each pair.
Shifts each lane to the right by the specified number of bits, shifting in zeros.
Converts a 128-bit vector interpreted as four 32-bit floating point numbers into a 128-bit vector of four 32-bit unsigned integers.
Saturating conversion of the two double-precision floating point lanes to two lower integer lanes using the IEEE convertToIntegerTowardZero function.
Converts high half of the smaller lane vector to a larger lane vector, zero extended.
Converts low half of the smaller lane vector to a larger lane vector, zero extended.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Lane-wise integer extended multiplication producing twice wider result than the inputs.
Shifts each lane to the right by the specified number of bits, shifting in zeros.
Performs a bitwise and of the two input 128-bit vectors, returning the resulting vector.
Bitwise AND of bits of a and the logical inverse of bits of b.
Returns true if any bit in a is set, or false otherwise.
Rust: fn v128_bitselect(v1: v128, v2: v128, c: v128) -> v128
Use the bitmask in c
to select bits from v1
when 1 and v2
when 0.
Loads a v128 vector from the given heap address.
Loads an 8-bit value from m and sets lane L of v to that value.
Load a single element and splat to all lanes of a v128 vector.
Loads a 16-bit value from m and sets lane L of v to that value.
Load a single element and splat to all lanes of a v128 vector.
Loads a 32-bit value from m and sets lane L of v to that value.
Load a single element and splat to all lanes of a v128 vector.
Load a 32-bit element into the low bits of the vector and sets all other bits to zero.
Loads a 64-bit value from m and sets lane L of v to that value.
Load a single element and splat to all lanes of a v128 vector.
Load a 64-bit element into the low bits of the vector and sets all other bits to zero.
Flips each bit of the 128-bit input vector.
Performs a bitwise or of the two input 128-bit vectors, returning the resulting vector.
Stores a v128 vector to the given heap address.
Stores the 8-bit value from lane L of v into m
Stores the 16-bit value from lane L of v into m
Stores the 32-bit value from lane L of v into m
Stores the 64-bit value from lane L of v into m
Performs a bitwise xor of the two input 128-bit vectors, returning the resulting vector.
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
Opcode location during prototyping.
Relaxed SIMD proposal
relaxed i8x16.swizzle(a, s)
selects lanes from a
using indices in s
,
indices in the range [0,15]
will select the i
-th element of a
, the result
for any out of range indices is implementation-defined (i.e. if the index is [16-255]
.
relaxed i32x4.trunc_f32x4_s
(relaxed version of i32x4.trunc_sat_f32x4_s
)
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32
(signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX
for signed and UINT32_MAX
for unsigned. The result of lanes which are out of bounds of INT32
or UINT32
is implementation defined, it can be either the saturated result or INT32_MAX
for signed and UINT32_MAX
for unsigned.
relaxed i32x4.trunc_f32x4_u
(relaxed version of i32x4.trunc_sat_f32x4_u
)
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32
(signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX
for signed and UINT32_MAX
for unsigned. The result of lanes which are out of bounds of INT32
or UINT32
is implementation defined, it can be either the saturated result or INT32_MAX
for signed and UINT32_MAX
for unsigned.
relaxed i32x4.trunc_f64x2_s_zero
(relaxed version of i32x4.trunc_sat_f64x2_s_zero
)
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32
(signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX
for signed and UINT32_MAX
for unsigned. The result of lanes which are out of bounds of INT32
or UINT32
is implementation defined, it can be either the saturated result or INT32_MAX
for signed and UINT32_MAX
for unsigned.
relaxed i32x4.trunc_f64x2_u_zero
(relaxed version of i32x4.trunc_sat_f64x2_u_zero
)
This instruction has the same behavior as the non-relaxed instruction for lanes that are in the range of an i32
(signed or unsigned depending on the instruction). The result of lanes which contain NaN is implementation defined, either 0 or INT32_MAX
for signed and UINT32_MAX
for unsigned. The result of lanes which are out of bounds of INT32
or UINT32
is implementation defined, it can be either the saturated result or INT32_MAX
for signed and UINT32_MAX
for unsigned.
Relaxed fused multiply-add
relaxed f32x4.madd(a, b, c) = a * b + c
where:
- the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
- the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Relaxed fused negative multiply-add
relaxed f32x4.nmadd(a, b, c) = -(a * b) + c
where:
- the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
- the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Relaxed fused multiply-add
relaxed f64x2.madd(a, b, c) = a * b + c
where:
- the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
- the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
Relaxed fused negative multiply-add
relaxed f64x2.nmadd(a, b, c) = -(a * b) + c
where:
- the intermediate a * b is be rounded first, and the final result rounded again (for a total of 2 roundings), or
- the entire expression evaluated with higher precision and then only rounded once (if supported by hardware).
i8x16.laneselect(a: v128, b: v128, m: v128) -> v128
Select lanes from a
or b
based on masks in m
. If each lane-sized mask in m
has all bits set or all bits unset, these instructions behave the same as v128.bitselect
. Otherwise, the result is implementation defined.
i16x8.laneselect(a: v128, b: v128, m: v128) -> v128
Select lanes from a
or b
based on masks in m
. If each lane-sized mask in m
has all bits set or all bits unset, these instructions behave the same as v128.bitselect
. Otherwise, the result is implementation defined.
i32x4.laneselect(a: v128, b: v128, m: v128) -> v128
Select lanes from a
or b
based on masks in m
. If each lane-sized mask in m
has all bits set or all bits unset, these instructions behave the same as v128.bitselect
. Otherwise, the result is implementation defined.
i64x2.laneselect(a: v128, b: v128, m: v128) -> v128
Select lanes from a
or b
based on masks in m
. If each lane-sized mask in m
has all bits set or all bits unset, these instructions behave the same as v128.bitselect
. Otherwise, the result is implementation defined.
Relaxed min
f32x4.min(a: v128, b: v128) -> v128
Return the lane-wise minimum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Relaxed max
f32x4.max(a: v128, b: v128) -> v128
Return the lane-wise maximum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Relaxed min
f64x2.min(a: v128, b: v128) -> v128
Return the lane-wise minimum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Relaxed max
f64x2.max(a: v128, b: v128) -> v128
Return the lane-wise maximum of two values. If either values is NaN, or the values are -0.0 and +0.0, the return value is implementation-defined.
Relaxed Rounding Q-format Multiplication
i16x8.q15mulr_s(a: v128, b: v128) -> v128
Returns the multiplication of 2 fixed-point numbers in Q15 format. If both inputs are INT16_MIN
, the result overflows, and the return value is implementation defined (either INT16_MIN
or INT16_MAX
).
Relaxed integer dot product
i16x8.dot_i8x16_i7x16_s(a: v128, b: v128) -> v128
Returns the multiplication of 8-bit elements (signed or unsigned) by 7-bit elements (unsigned) with accumulation of adjacent products. The i32x4
versions allows for accumulation into another vector.
When the second operand of the product has the high bit set in a lane, that lane's result is implementation defined.
Relaxed integer dot product
i32x4.dot_i8x16_i7x16_add_s(a: v128, b:v128, c:v128) -> v128
Returns the multiplication of 8-bit elements (signed or unsigned) by 7-bit elements (unsigned) with accumulation of adjacent products. The i32x4
versions allows for accumulation into another vector.
When the second operand of the product has the high bit set in a lane, that lane's result is implementation defined.
Relaxed BFloat16 dot product
i32x4.dot_i8x16_i7x16_add_s(a: v128, b:v128, c:v128) -> v128
BFloat16 is a 16-bit floating-point format that represents the IEEE FP32 numbers truncated to the high 16 bits. This instruction computes a FP32 dot product of 2 BFloat16 with accumulation into another FP32.
atomically load 1 byte and zero-extend i8 to i32
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
atomically load 2 bytes and zero-extend i16 to i32
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
atomically load 4 bytes as i32
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
atomically load 1 byte and zero-extend i8 to i64
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
atomically load 2 bytes and zero-extend i16 to i64
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
atomically load 4 bytes and zero-extend i32 to i64
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
atomically load 8 bytes as i64
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
wrap i32 to i8 and atomically store 1 byte
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
wrap i32 to i16 and atomically store 2 bytes
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
(no conversion) atomically store 4 bytes
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
wrap i64 to i8 and atomically store 1 byte
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
wrap i64 to i16 and atomically store 2 bytes
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
wrap i64 to i32 and atomically store 4 bytes
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
(no conversion) atomically store 8 bytes
Atomic load/store memory accesses behave like their non-atomic counterparts, with the exception that the ordering of accesses is sequentially consistent.
8-bit sign-agnostic addition
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic addition
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic addition
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic addition
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
64-bit sign-agnostic addition
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic addition
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
64-bit sign-agnostic addition
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic subtraction
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic subtraction
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic subtraction
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic subtraction
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic subtraction
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic subtraction
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
64-bit sign-agnostic subtraction
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic bitwise and
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic bitwise and
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic bitwise and
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic bitwise and
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic bitwise and
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic bitwise and
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
64-bit sign-agnostic bitwise and
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic bitwise inclusive or
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic bitwise inclusive or
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic bitwise inclusive or
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic bitwise inclusive or
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic bitwise inclusive or
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic bitwise inclusive or
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
64-bit sign-agnostic bitwise inclusive or
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic bitwise exclusive or
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic bitwise exclusive or
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic bitwise exclusive or
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
8-bit sign-agnostic bitwise exclusive or
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
16-bit sign-agnostic bitwise exclusive or
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
32-bit sign-agnostic bitwise exclusive or
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
64-bit sign-agnostic bitwise exclusive or
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 4 bytes, Write: 4 bytes
Returns: as i32
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 1 byte, Write: 1 byte
Returns: zero-extended i8 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 2 bytes, Write: 2 bytes
Returns: zero-extended i16 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 4 bytes, Write: 4 bytes
Returns: zero-extended i32 to i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
nop
Read: 8 bytes, Write: 8 bytes
Returns: as i64
Atomic read-modify-write (RMW) operators atomically read a value from an address, modify the value, and store the resulting value to the same address. All RMW operators return the value read from memory before the modify operation was performed.
The RMW operators have two operands, an address and a value used in the modify operation.
Load as loaded: 1 byte
Compare expected with loaded: `expected` wrapped from i32 to i8, 8-bit compare equal
Conditionally Store replacement: wrapped from i32 to i8, store 1 byte
Return loaded: zero-extended from i8 to i32
Load as loaded: 2 bytes
Compare expected with loaded: `expected` wrapped from i32 to i16, 16-bit compare equal
Conditionally Store replacement: wrapped from i32 to i16, store 2 bytes
Return loaded: zero-extended from i8 to i32
Load as loaded: 4 bytes
Compare expected with loaded: 32-bit compare equal
Conditionally Store replacement: store 4 bytes
Return loaded: as i32
Load as loaded: 1 byte
Compare expected with loaded: `expected` wrapped from i64 to i8, 8-bit compare equal
Conditionally Store replacement: wrapped from i64 to i8, store 1 byte
Return loaded: zero-extended from i8 to i64
Load as loaded: 2 bytes
Compare expected with loaded: `expected` wrapped from i64 to i16, 16-bit compare equal
Conditionally Store replacement: wrapped from i64 to i16, store 2 bytes
Return loaded: zero-extended from i16 to i64
Load as loaded:4 bytes
Compare expected with loaded: `expected` wrapped from i64 to i32, 32-bit compare equal
Conditionally Store replacement: wrapped from i64 to i32, store 4 bytes
Return loaded: zero-extended from i32 to i64
Load as loaded: 8 bytes
Compare expected with loaded: 64-bit compare equal
Conditionally Store replacement: 8 bytes
Return loaded: as i64